This invention relates to a semiconductor device, and more particularly to, a semiconductor device having a Lead on Chip structure in which conductive leads are mounted on the surface of a semiconductor chip.
According to the demand of high-density packaging of a mass storage memory like a Dynamic Random Access Memory (DRAM), a Lead on Chip (LOC) structure, which allows a relatively large-scale semiconductor chip to be stored in a relatively small package, has been adopted.
A conventional semiconductor device comprises a semiconductor chap having bonding pads thereon, conductive leads, each of which comprises an inner lead and an outer lead, adhesive tapes by which each of the inner leads of the leads are stuck to the surface of the semiconductor chip, bonding wires by which each of the leads are electrically connected to each corresponding bonding pad, and a molding resin by which the semiconductor chip, the inner leads and other parts are molded. Most part of each outer lead protrudes out of the molding resin, and extends in J-shape from both sides thereof toward the back side thereof. The outer leads are used as electrical terminals for connecting the semiconductor chip to other electrical circuits.
Another type of a semiconductor device having a Chip Scale Package (CSP) has been proposed. Such a CSP type semiconductor device comprises a semiconductor chip having bonding pads thereon, conductive leads, each of which comprises an inner lead and an outer lead, a cover film stuck to one plane of the semiconductor chip, so that the bonding pads are exposed through the openings of the cover film. The inner leads, which are aligned radially around the bonding pads, are attached to the cover film. Each inner lead is electrically connected to each corresponding bonding pad by bonding wires. Both side planes of the semiconductor chip, a spacing between the back side of the outer leads and the cover film, and other parts are molded by a molding resin, whereas the other plane of the semiconductor chip is not molded. Each lead is bent in S-shape at the boundary of the inner lead and the outer lead, and the outer lead extends, in parallel along the one plane or the semiconductor chip.
In the first mentioned conventional LOC type semiconductor device, however, there is a disadvantage in that since each lead is not designed to have a step between the inner lead and the outer lead, so that a top portion of each looped bonding wire is positioned above the top surface of each lead. Therefore, the bonding wires are more likely to be given an impact from outside. Thereby, resulting in that the alignment of the looped bonding wires is easily influenced by just a slight shock, then a short-circuit or a disconnection of the bonding wire is likely to occur. Therefore, its handling is more difficult.
Another disadvantage of the first mentioned conventional semiconductor device is that stacking semiconductor devices is impossible since each outer lead is not exposed on the surface of the semiconductor device. Therefore, the semiconductor device is not applicable to such multi-stacked structure. Such disadvantage is a common one in the second mentioned proposed semiconductor device, because the surface of the outer lead thereof may come into contact with the exposed plane of underlaid semiconductor chip of another semiconductor device directly, when they are stacked.